The high-density and medium+ density STM8L15xx6/8 ultra-low-power devices feature an enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low-power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming. All high-density and medium+ density STM8L15xx6/8 microcontrollers feature embedded data EEPROM and low-power low-voltage single-supply program Flash memory. The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit ADC, two DACs, two comparators, a real-time clock, four 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two SPIs, an I2C interface, and three USARTs. A 8x40 or 4x44-segment LCD is available on the STM8L152x8 devices. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.
All features
Operating conditions
Operating power supply: 1.65 to 3.6 V (without BOR), 1.8 to 3.6 V (with BOR)
Temp. range: -40 to 85, 105 or 125 °C
Low-power features
5 low-power modes: Wait, Low-power run (5.9 μA), Low-power wait (3 μA), Active-halt with full RTC (1.4 μA), Halt (400 nA)
Consumption: 200 μA/MHz+330 μA
Fast wake up from Halt mode (4.7 μs)
Ultra low leakage per I/0: 50 nA
Advanced STM8 core
Harvard architecture and 3-stage pipeline
Max freq: 16 MHz, 16 CISC MIPS peak
Up to 40 external interrupt sources
Reset and supply management
Low-power, ultra safe BOR reset with five programmable thresholds
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