STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm? Cortex?-M7 32-bit RISC core operating at up to 480 MHz. The Cortex? -M7 core features a floating point unit (FPU) which supports Arm? double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security. STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.
All features
Core
32-bit Arm? Cortex?-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
Up to 2 Mbytes of Flash memory with read-while-write support
Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
Dual mode Quad-SPI memory interface running up to 133 MHz
Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode
CRC calculation unit
Security
ROP, PC-ROP, active tamper
General-purpose input/outputs
Up to 168 I/O ports with interrupt capability
Reset and power management
3 separate power domains which can be independently clock-gated or switched off:
D1: high-performance capabilities
D2: communication peripherals and timers
D3: reset/clock control/power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode (6 configurable ranges)
Backup regulator (~0.9 V)
Voltage reference for analog peripheral/VREF+
Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging
Low-power consumption
VBAT battery operating mode with charging capability
CPU and domain power state monitoring pins
2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)